With increase of the number of transistors mounted in a CPU (Central Processing Unit), there has been a problem in that an error is frequently generated in a register file mounted in the CPU.
Hitherto, it is general to employ a method that detects an error by providing an odd or even parity for every several bit when detecting an error. However, by the method of parity, although an error can be detected, the error can not be corrected. Consequently, when an error is detected when accessing to a register file or the like, it is necessary to re-execute memory access, and this largely affects the performance of the CPU.
Consequently, it has been desired not only to detect an error of data, but also to correct the data in the register file. It is desirable to correct the error by using an ECC data (Error Checking and Correction data).
However, there is a problem in that the processing speed of a CPU is largely reduced when the ECC data is simply replaced instead of the parity data which has been conventionally added to the data in a register file.
Further, there is a patent document described below as for an error correcting method.    [Patent Document 1] Japanese Laid-open Patent Publication No. 05-20215